AMCC PPC405 Spécifications télécharger pdf (Page 11)

405GP – Power PC 405GP Embedded Processor

AMCC 11

Revision 2.01 – January 6, 2005

Data Sheet

• Peripheral Device pacing with external “Ready”

• External master interface

- Write posting from external master

- Read prefetching on PLB for external master reads

- Bursting capable from external master

- Allows external master access to all non-EBC PLB slaves

- External master can control EBC slaves for own access and control

DMA Controller

• Supports the following transfers:

- Memory-to-memory transfers

- Buffered peripheral to memory transfers

- Buffered memory to peripheral transfers

• Four channels

• Scatter/gather capability for programming multiple DMA operations

• 8-, 16-, 32-bit peripheral support (OPB and external)

• 32-bit addressing

• Address increment or decrement

• Internal 32-byte data buffering capability

• Supports internal and external peripherals

• Support for memory mapped peripherals

• Support for peripherals running on slower frequency buses

Serial Interface

• One 8-pin UART and one 4-pin UART interface provided

• Selectable internal or external serial clock to allow a wide range of baud rates

• Register compatibility with NS16550 register set

• Complete status reporting capability

• Transmitter and receiver are each buffered with 16-byte FIFOs when in FIFO mode

• Fully programmable serial-interface characteristics

• Supports DMA using internal DMA engine

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AMCC PPC405 Spécifications Page 11